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1/24 preliminary data march 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. M59BW102 1 mbit (64kb x16, burst) low voltage flash memory n 2.7 to 3.6v supply voltage for program, erase and read operations n sequential cycle time: 25ns n random access time n programming time: 10s typical n interleaved access time: 16ns n continuous memory interleaving C unlimited linear access data output n program/erase controller (p/e.c.) C program word-by-word C status register bits n low power consumption C stand-by and automatic stand-by n 100,000 program/erase cycles n 20 years data retention C defectivity below 1ppm/year n electronic signature C manufacturer code: 20h C device code: c1h description the M59BW102 is a non-volatile memory that may be erased electrically at the chip level and pro- grammed in-system on a word-by-word basis us- ing only a single 3v v cc supply. for program and erase operations the necessary high voltages are generated internally. the device can also be pro- grammed in standard programmers. the device can be programmed and erased over 100,000 cycles. instructions for read/reset, auto select for read- ing the electronic signature, programming and chip erase are written to the device in cycles of commands to a command interface using stan- dard microprocessor write timings. the M59BW102 features an interleaved access mo- dality which allows extremely fast access time. the device is offered in tsop40 (10 x 14mm) package. figure 1. logic diagram ai02763b 16 a0-a15 w dq0-dq15 v cc M59BW102 e v ss 16 g ale tsop40 (n) 10 x 14mm
M59BW102 2/24 figure 2. tsop connections dq6 dq3 dq2 dq13 dq8 dq7 dq10 dq9 a14 a8 a11 a10 a4 a15 a9 g a7 a2 dq1 dq0 a0 a1 a3 ale w e dq14 nc v cc dq15 ai02764b M59BW102 10 1 11 20 21 30 31 40 v ss a13 a12 a6 a5 dq11 dq12 dq5 dq4 v ss command interface instructions, made up of commands written in cy- cles, can be given to the program/erase controller through a command interface (c.i.). for added data protection, program or erase execution starts after 4 or 6 cycles. the first, second, fourth and fifth cycles are used to input coded cycles to the c.i. this coded sequence is the same for all pro- gram/erase controller instructions. the 'com- mand' itself and its confirmation, when applicable, are given on the third, fourth or sixth cycles. any incorrect command or any improper command se- quence will reset the device to read array mode. instructions four instructions are defined to perform read ar- ray, auto select (to read the electronic signature), program, chip erase. the internal p/e.c. auto- matically handles all timing and verification of the program and erase operations. the status regis- ter data polling, toggle and error bits may be read at any time, during programming or erase, to mon- itor the progress of the operation. instructions are composed of up to six cycles. the first two cycles input a coded sequence to the command interface which is common to all in- structions (see table 7). the third cycle inputs the instruction set-up command. subsequent cycles output the addressed data or electronic signature for read operations. in order to give additional data protection, the instructions for program and chip erase require further command inputs. for a program instruction, the fourth command cycle in- puts the address and data to be programmed. for an erase instruction, the fourth and fifth cycles in- put a further coded sequence before the com- mand confirmation on the sixth cycle. table 1. signal names a0-a15 address inputs dq0-dq7 data inputs/outputs, command inputs dq8-dq15 data inputs/outputs e chip enable g output enable w write enable ale address latch enable v cc supply voltage v ss ground nc not connected internally organization the M59BW102 is organized as 64k x16 bits. the memory uses the address inputs a0-a15 and the data inputs/outputs dq0-dq15. memory control is provided by chip enable e , output enable g , address latch enable ale and write enable w in- puts. erase and program operations are controlled by an internal program/erase controller (p/e.c.). status register data output on dq7 provides a data polling signal, and dq6 and dq2 provide toggle signals to indicate the state of the p/e.c operations. bus operations the following operations can be performed using the appropriate bus cycles: read (array, electron- ic signature), write command, output disable, standby. see tables 3 and 4.
3/24 M59BW102 signal descriptions see figure 1 and table 1. address inputs (a0-a15). the address inputs for the memory array are latched during a write op- eration on the falling edge of chip enable e or write enable w . when a9 is raised to v id , either a read electronic signature manufacturer or device code is enabled depending on the combination of levels on a0 and a1. data inputs/outputs (dq0-dq15). the input is data to be programmed in the memory array or a command to be written to the c.i. both are latched on the rising edge of chip enable e or write en- able w . the output is data from the memory array, the electronic signature manufacturer or device codes, the status register data polling bit dq7, the toggle bits dq6 and dq2, the error bit dq5 or the erase timer bit dq3. outputs are valid when chip enable e and output enable g are ac- tive. the output is high impedance when the chip is deselected or the outputs are disabled. chip enable (e ). the chip enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. e high deselects the memory and reduces the power consumption to the standby level. e can also be used to control writing to the command register and to the memo- ry array, while w remains at a low level. table 2. absolute maximum ratings (1) note: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other condition s above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi - tions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant qual- ity documents. 2. minimum voltage may undershoot to C2v during transition and for less than 20ns. table 3. user bus operations (1)) note: 1. x = v il or v ih . table 4. read electronic signature (following as instruction or with a9 = v id ) symbol parameter value unit t a ambient operating temperature 0 to 70 c t bias temperature under bias C50 to 125 c t stg storage temperature C65 to 150 c v io (2) input or output voltage C0.6 to 5 v v cc supply voltage C0.6 to 5 v v (a9, e , g ) (2) a9, e , g voltage C0.6 to 13.5 v operation e g w ale a0 a1 a6 a9 a12 a15 dq15-dq0 non linear access mode v il v il v ih pulse x x x x x x data output linear access cycle v il rising edge v ih v il x x x x x x data output write word v il v ih v il v ih a0 a1 a6 a9 a12 a15 data input output disable v il v ih v ih v ih x x x x x x hi-z standby v ih x x x x x x x x x hi-z code e g w a0 a1 other address dq15-dq8 dq7-dq0 manufact. code v il v il v ih v il v il don't care 00h 20h device code v il v il v ih v ih v il don't care 00h c1h
M59BW102 4/24 reached by the counters they start again from the first memory address and continue. the M59BW102 will provide data output during the la cycle determined by g signal. each time ale signal is pulsed and g signal is high, while the current address is loaded into the counters, the output buffers are put in hi-z condi- tion and remain in this condition until the first new valid data comes. the M59BW102 operation in la and nla modes is explained in figure 3 and the block diagram is shown in figure 4. write. write operations are used to give instruc- tion commands to the memory or to latch input data to be programmed. a write operation is initi- ated when address latch enable (ale) is high, chip enable e is low and write enable w is low with output enable g high. addresses are latched on the falling edge of w or e whichever occurs last. commands and input data are latched on the rising edge of w or e whichever occurs first. output disable. the data outputs are high im- pedance when the output enable g and the ad- dress latch enable (ale) are both high with write enable w high. standby. the memory is in standby when chip enable e is high and the p/e.c. is idle. the power consumption is reduced to the standby level and the outputs are high impedance, independent of the output enable g , the address latch enable (ale) or the write enable w inputs. electronic signature. two codes identifying the manufacturer and the device can be read from the memory. the manufacturer's code for stmicroelectronics is 20h, the device code is c1h. these codes allow programming equipment or ap- plications to automatically match their interface to the characteristics of the M59BW102. the elec- tronic signature is output by a read operation when the voltage applied to a9 is at v id and ad- dress inputs a1 is low. the manufacturer code is output when the address input a0 is low and the device code when this input is high. other ad- dress inputs are ignored. the codes are output on dq0-dq7. the electronic signature can also be read, without raising a9 to v id , by giving the memory the in- struction as. the codes are output on dq0-dq7 with dq8-dq15 at 00h. output enable (g ). the output enable gates the outputs through the data buffers during a read op- eration. when g and ale are both high the out- puts are high impedance. write enable (w ). this input controls writing to the command register and address and data latches. address latch enable (ale). this input con- trols the latching of address for reading. when pulsed, the device operates in the random or non linear access mode. v cc supply voltage. the power supply for all operations (read, program and erase). v ss ground. v ss is the reference for all voltage measurements. device operations see tables 3 and 4. read (non linear access mode and linear ac- cess cycle). the device is internally organized in two memory banks (named even and odd bank). a0 address bit is asserted as "priority" bit, so that when a0 = 0 the even bank is the current memory array under selection and the odd bank is masked. when a0 = 1 the odd bank is the current array un- der selection and even bank is masked. to begin a random (or non linear) access mode (nla), ale is pulsed high and e is asserted low. two internal 15 bit counters store the current ad- dress for the odd and even banks and increment alternatively, under the priority bit control, during each subsequent cycle called sequential (or lin- ear) address cycle (la). the linear cycle (la) can be terminated if a new nla starts or if e is assert- ed high, putting the device in stand-by mode. in this last case the linear cycle can be resumed if e is asserted low again and ale is low. during the la mode all the memory can be swept, as there is no physical limits to the linear access output. when the last address of the memory is table 5. commands hex code command 00h invalid/reserved 10h chip erase confirm 20h reserved 80h set-up erase 90h read electronic signature a0h program f0h read array/reset table 6. polling and toggle bits mode dq7 dq6 dq2 program dq7 toggle 1 erase 0 toggle toggle
5/24 M59BW102 figure 3. non linear and linear access cycle timing diagram ai02766b ale g e a0-a15 address (odd) address (even) addr + 1 addr + 2 addr + 3 even even odd odd odd address (even) addr + 2 addr + 4 addr + 1 clkout dq0-dq15 cntr even addr + 1 addr + 3 address (odd) cntr odd non linear linear linear linear non linear addr + 2 odd even addr + 1 addr + 2 addr+3 14 14 resume (linear)
M59BW102 6/24 figure 4. block diagram ai02765 odd matrix (16 x 32k) even matrix (16 x 32k) g e ale multiplexer even counter output buffer odd counter dq0-dq15 a1-a15 logic a0 instructions and commands the command interface latches commands writ- ten to the memory. instructions are made up from one or more commands to perform read memory array, read electronic signature, program, chip erase. commands are made of address and data sequences. the instructions require from 1 to 6 cy- cles, the first or first three of which are always write operations used to initiate the instruction. they are followed by either further write cycles to confirm the first command or execute the command imme- diately. command sequencing must be followed exactly. any invalid combination of commands will reset the device to read array. the increased number of cycles has been chosen to assure max- imum data security. instructions are initialised by two initial coded cycles which unlock the com- mand interface. in addition, for erase, instruction confirmation is again preceded by the two coded cycles. status register bits p/e.c. status is indicated during execution by data polling on dq7, detection of toggle on dq6 and dq2, or error on dq5 and erase timer dq3 bits. any read attempt from any address during pro- gram or erase command execution will automati- cally output these five status register bits. the p/ e.c. automatically sets bits dq2, dq3, dq5, dq6 and dq7. other bits (dq0, dq1 and dq4) are re- served for future use and should be masked. see table 8. data polling bit (dq7). when programming op- erations are in progress, this bit outputs the com- plement of the bit being programmed on dq7. during erase operation, it outputs a '0'. after com- pletion of the operation, dq7 will output the bit last programmed or a '1' after erasing. data polling is valid and only effective during p/e.c. operation, that is after the fourth w pulse for programming or after the sixth w pulse for erase. see figure 11 for the data polling waveforms and figure 12 for the data polling flowchart. a valid address is the ad- dress being programmed or any address while erasing the chip. toggle bit (dq6). when programming or eras- ing operations are in progress, successive at- tempts to read dq6 will output complementary
7/24 M59BW102 data. dq6 will toggle following toggling of either g , or e when g is low. the operation is completed when two successive reads yield the same output data. the next read will output the bit last pro- grammed or a '1' after erasing. the toggle bit dq6 is valid only during p/e.c. operations, that is after the fourth w pulse for programming or after the sixth w pulse for erase. see figure 13 for toggle bit flowchart and figure 14 for toggle bit wave- forms. toggle bit (dq2). this toggle bit, together with dq6, can be used to determine the device status during the erase operations. during chip erase a read operation will cause dq2 to toggle since chip is being erased. dq2 will be set to '1' during pro- gram operation and when erase is complete. error bit (dq5). this bit is set to '1' by the p/e.c. when there is a failure of programming or chip erase that results in invalid data in the memory. in case of an error in program, the chip must be dis- carded. the dq5 failure condition will also appear if a user tries to program a '1' to a location that is previously programmed to '0'. the error bit resets after a read/reset (rd) instruction. in case of success of program or erase, the error bit will be set to '0'. erase timer bit (dq3). this bit is set to '0' by the p/e.c. when the erase command has been en- tered to the command interface and it is awaiting the erase start. when the erase timeout period is finished, after 50s to 120s, dq3 returns to '1'. coded cycles the two coded cycles unlock the command inter- face. they are followed by an input command or a confirmation command. the coded cycles consist of writing the data aah at address 555h during the first cycle. during the second cycle the coded cy- cles consist of writing the data 55h at address 2aah. address lines a0 to a10 are valid; other ad- dress lines are 'don't care'. the coded cycles hap- pen on first and second cycles of the command write or on the fourth and fifth cycles. table 7. instructions (1) note: 1. commands not interpreted in this table will default to read array mode. 2. a wait of 10s is necessary after a read/reset command if the memory was in an erase or program mode before starting any new operation. 3. x = don't care. 4. the first cycles of the rd or as instructions are followed by read operations. any number of read cycles can occur after the com- mand cycles. 5. signature address bits a0, a1, at v il will output manufacturer code (20h). address bits a0 at v ih and a1, at v il will output device code. 6. for coded cycles address inputs a11-a16 are don't care. 7. read data polling, toggle bits until erase completes. mne. instr. cyc. 1st cyc. 2nd cyc. 3rd cyc. 4th cyc. 5th cyc. 6th cyc. 7th cyc. rd (2,4) read/reset memory array 1+ addr. (3,6) x read memory array until a new write cycle is initiated. data f0h 3+ addr. (3,6) 555h 2aah x read memory array until a new write cycle is initiated. data aah 55h f0h as (4) auto select 3+ addr. (3,6) 555h 2aah 555h read electronic signature until a new write cycle is initiated. see note 5. data aah 55h 90h pg program 4 addr. (3,6) 555h 2aah 555h program address read data polling or toggle bit until program completes. data aah 55h a0h program data ce chip erase 6 addr. (3,6) 555h 2aah 555h 555h 2aah 555h note 7 data aah 55h 80h aah 55h 10h
M59BW102 8/24 table 8. status register bits note: logic level '1' is high, '0' is low. -0-1-0-0-0-1-1-1-0- represent bit value in successive read operations. dq name logic level definition note 7 data polling '1' erase complete indicates the p/e.c. status, check during program or erase, and on completion before checking bits dq5 for program or erase success. '0' erase on-going dq program complete dq program on-going 6 toggle bit '-1-0-1-0-1-0-1-' erase or program on-going successive reads output complementary data on dq6 while programming or erase operations are on-going. dq6 remains at constant level when p/e.c. operations are completed. dq program complete '-1-1-1-1-1-1-1-' erase complete 5 error bit '1' program or erase error this bit is set to '1' in the case of programming or erase failure. '0' program or erase on-going 4 reserved 3 erase time bit '1' erase timeout period expired p/e.c. erase operation has started. '0' erase timeout period on- going 2 toggle bit '-1-0-1-0-1-0-1-' chip erase indicates the erase status. '1' program on-going or erase complete 1 reserved 0 reserved instructions see table 7. read/reset (rd) instruction. the read/reset instruction consists of one write cycle giving the command f0h. it can be optionally preceded by the two coded cycles. subsequent read opera- tions will read the memory array addressed and output the data read. read/reset is not accepted in program/erase operation unless a fail occurred. auto select (as) instruction. this instruction uses the two coded cycles followed by one write cycle giving the command 90h to address 555h for command set-up. a subsequent read will output the manufacturer code and the device code de- pending on the levels of a0 and a1. the manufac- turer code, 20h, is output when the addresses lines a0 and a1 are low, the device code, c1h is output when a0 is high with a1 low. program (pg) instruction. this instruction uses four write cycles. the program command a0h is written to address 555h on the third cycle after two coded cycles. a fourth write operation latches the address on the falling edge of w or e and the data to be written on the rising edge and starts the p/ e.c. read operations output the status register bits after the programming has started. memory programming is made only by writing '0' in place of '1'. status bits dq6 and dq7 determine if pro- gramming is on-going and dq5 allows verification of any possible error. chip erase (ce) instruction. this instruction uses six write cycles. the set-up command 80h is writ-
9/24 M59BW102 figure 6. ac testing load circuit ai01119 1.3v out c l = 30pf c l includes jig capacitance 3.3k w 1n914 device under test table 9. ac measurement conditions load capacitance (c l ) 30pf input rise and fall times 10ns input pulse voltages 0 to 3v input and output timing ref. voltages 1.5v figure 5. ac testing input output waveform ai01417 3v 0v 1.5v table 10. capacitance (1) (t a = 25 c, f = 1 mhz) note: 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0v 6pf c out output capacitance v out = 0v 12 pf ten to address 555h on the third cycle after the two coded cycles. the chip erase confirm command 10h is similarly written on the sixth cycle after an- other two coded cycles. if the second command given is not an erase confirm or if the coded cy- cles are wrong, the instruction aborts and the de- vice is reset to read array. it is not necessary to program the array with 0000h first as the p/e.c. will automatically do this before erasing it to ffffh. read operations after the sixth rising edge of w or e output the status register bits. during the execution of the erase by the p/e.c., data polling bit dq7 returns '0', then '1' on completion. the toggle bits dq2 and dq6 toggle during erase operation and stop when erase is completed. after completion the status register bit dq5 returns '1' if there has been an erase failure. power supply power up the memory command interface is reset on pow- er up to read array. either e or w must be tied to v ih during power up to allow maximum security and the possibility to write a command on the first rising edge of e and w . any write cycle initiation is blocked when v cc is below v lko . supply rails normal precautions must be taken for supply volt- age decoupling; each device in a system should have the v cc rail decoupled with a 0.1f capacitor close to the v cc and v ss pins. the pcb trace widths should be sufficient to carry the v cc pro- gram and erase currents required.
M59BW102 10/24 table 11. dc characteristics (t a = 0 to 70c; v cc = 3.0v to 3.6v) note: 1. sampled only, not 100% tested. table 12. sequential read mode ac characteristics ( t a = 0 to 70c) note: 1. this timing refers to a load capacitance (c l ) of 30pf. if c l is higher, add 1 ns for each extra 10pf. symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current (read) e = v il , g = v ih , f = 6mhz 10 ma i cc2 supply current (standby) ale, e = v cc 0.2v 100 a i cc3 (1) supply current (program or erase) byte program or chip erase in progress 20 ma v il input low voltage C0.5 0.8 v v ih input high voltage 2v cc + 0.3 v v ol output low voltage i ol = 1.8ma 0.45 v v oh output high voltage i oh = C100a v cc C 0.4v v v id a9, e , g high voltage 11.5 12.5 v i id a9, e , g high current a9, e , g = v id 100 a v lko (1) supply voltage (erase and program lock-out) 1.8 2.3 v symbol alt parameter test condition M59BW102 unit 25 v cc = 3.0v to 3.6v min typ max t cycle t cy sequential cycle e = v il , ale = v il 25 ns t ghgl t gw output enable high to output enable low g = pulse 13 ns t glgh t gl output enable low to output enable high g = pulse 12 ns t ghel t att output enable high to chip enable low C2 ns t gheh t sby output enable high to chip enable high C2 ns t ehalh t av chip enable high to address latch enable high 3ns t ghalh t gs output enable high to address latch enable high (following cycle) 0ns t ghqv (1) t gacc output enable high to output valid 20 ns t elqv (1) t eacc chip enable low to output valid 20 ns t ehqz t edf chip enable high to output hi-z 12 ns t alhqz t adf address latch enable high to output hi-z 20 ns
11/24 M59BW102 table 13. random read mode ac characteristics ( t a = 0 to 70c) note: 1. this timing refers to a load capacitance (c l ) of 30pf. if c l is higher, add 1ns for each extra 10pf. symbol alt parameter test condition M59BW102 unit 25 v cc = 3.0v to 3.6v min typ max t alhall t alw address latch enable high to address latch enable low ale = pulse 10 ns t elall t e chip enable low to address latch enable low 10 ns t axall t as address transition to address latch enable low 6ns t ehalh t elv chip enable high to address latch enable high 3ns t allgl t ag address latch enable low to output enable low 7.5 ns t ghalh t qp output enable high to address latch enable high 0ns t ghgl t gw output enable high to output enable low g = pulse 14 ns t glgh t gl output enable low to output enable high 48 ns t glqv (1) t gacc output enable low to output valid 30 ns t elqv (1) t eacc chip enable low to output valid 55 ns t ghel t ge output enable high to chip enable low C2 ns t ehqz t edf chip enable high to output hi-z 12 ns t alhqz t adf address latch enable high to output hi-z 20 ns t qvgh t qv output valid to output enable high 10 ns t gheh t ge output enable high to chip enable high 0 ns t elgl t egl chip enable low to output enable low 13 ns t ehqv chip enable high to data hold 0 ns t allax address latch enable low to address transition 30 ns
M59BW102 12/24 figure 7. sequential cycle waveforms figure 8. random mode waveforms ai02767b ale e g a0-a15 dq0-dq15 tcycle tehqz tghel tghgl telqv talhqz tghalh tghqv tgheh tglgh tehqv tehalh ai02768b ale e g telqv a0-a15 dq0-dq15 tallgl tehqz tghgl taxall telall tqvgh talhqz tghalh talhall tglqv tghel tgheh tehalh tehqv tglgh tallax telgl
13/24 M59BW102 table 14. write ac characteristics, write enable controlled (t a = 0 to 70c) symbol alt parameter M59BW102 unit 25 v cc = 3.0v to 3.6v min max t avav t wc address valid to next address valid 55 ns t elwl t cs chip enable low to write enable low 0 ns t wlwh t wp write enable low to write enable high 30 ns t dvwh t ds input valid to write enable high 25 ns t whdx t dh write enable high to input transition 0 ns t wheh t ch write enable high to chip enable high 0 ns t whwl t wph write enable high to write enable low 20 ns t avw l t as address valid to write enable low 0 ns t wlax t ah write enable low to address transition 35 ns t ghwl output enable high to write enable low 0 ns t vchel t vcs v cc high to chip enable low 50 s t whgl t oeh write enable high to output enable low 0 ns figure 9. write ac waveforms, w controlled note: address are latched on the falling edge of w , data is latched on the rising edge of w ; ale must be high. ai02769 e g w a0-a15 dq0-dq15 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl
M59BW102 14/24 table 15. write ac characteristics, chip enable controlled (t a = 0 to 70c) symbol alt parameter M59BW102 unit 25 v cc = 3.0v to 3.6v min max t avav t wc address valid to next address valid 55 ns t wlel t ws write enable low to chip enable low 0 ns t eleh t cp chip enable low to chip enable high 30 ns t dveh t ds input valid to chip enable high 25 ns t ehdx t dh chip enable high to input transition 0 ns t ehwh t wh chip enable high to write enable high 0 ns t ehel t cph chip enable high to chip enable low 20 ns t ave l t as address valid to chip enable low 0 ns t elax t ah chip enable low to address transition 35 ns t ghel output enable high to chip enable low 0 ns t vchwl t vcs v cc high to write enable low 50 s t ehgl t oeh chip enable high to output enable low 0 ns figure 10. write ac waveforms, e controlled note: address are latched on the falling edge of e , data is latched on the rising edge of e ; ale must be high. ai02770 e g w a0-a15 dq0-dq15 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel
15/24 M59BW102 figure 11. write ac waveforms, w controlled and address latch enable pulsed note: address are latched on the falling edge of w , data is latched on the rising edge of w. ai03041b e g w a0-a15 dq0-dq15 valid valid v cc tvchel twheh twhwl telwl tavall twhgl tallax twhdx tavav tdvwh twlwh tghwl ale telall talhwl twhall tehgl table 16. write ac characteristics, write enable controlled and address latch enable pulsed (t a = 0 to 70c) note: 1. these parameters are applicable only if the following cycle is for the same device. symbol alt parameter M59BW102 unit 25 v cc = 3.0v to 3.6v min max t avav t wc address valid to next address valid 55 ns t elwl t cs chip enable low to write enable low 0 ns t wlwh t wp write enable low to write enable high 30 ns t dvwh t ds input valid to write enable high 25 ns t whdx t dh write enable high to input transition 0 ns t wheh t ch write enable high to chip enable high 0 ns t whwl (1) t wph write enable high to write enable low 20 ns t ghwl output enable high to write enable low 0 ns t vchel t vcs v cc high to chip enable low 50 s t whgl t oeh write enable high to output enable low 0 ns t alhwl address latch enable high to write enable low 10 ns t ava ll address valid to address latch enable low 5 ns t elall chip enable low to address latch enable low 10 ns t allax address latch enable low to address transition 35 ns t whall (1) write enable high to address latch enable low 50 ns t ehgl chip enable high to output enable low 10 ns
M59BW102 16/24 figure 12. suspend and resume linear cycle waveforms with bus idle ai03248 ale e g a0-a15 dq0-dq15 tehalh tallel tgheh odd even odd even fetch idle fetch idle fetch idle table 17. suspend and resume last linear cycle characteristics (t a = 0 to 70c) symbol alt parameter M59BW102 unit 25 v cc = 3.0v to 3.6v min max t allel address latch enable low to chip enable low 15 ns
17/24 M59BW102 figure 13. suspend and resume linear cycle waveforms without bus idle ai03249 ale e g a0-a15 dq0-dq15 tehalh tallel tgheh odd odd even even fetch fetch fetch fetch idle idle idle table 18. suspend and resume next linear cycle characteristics (t a = 0 to 70c) symbol alt parameter M59BW102 unit 25 v cc = 3.0v to 3.6v min max t allel address latch enable low to chip enable low 15 ns
M59BW102 18/24 table 19. data polling and toggle bit ac characteristics (1) (t a = 0 to 70c) note: 1. all other timings are defined in read ac characteristics table. symbol parameter M59BW102 unit 25 v cc = 3.0v to 3.6v min max t whq7v write enable high to dq7 valid (program, w controlled) 10 2400 s write enable high to dq7 valid (chip erase, w controlled) 1 30 sec t ehq7v chip enable high to dq7 valid (program, e controlled) 10 2400 s chip enable high to dq7 valid (chip erase, e controlled) 1 30 sec t q7vqv dq7 valid to output valid (data polling) 25 ns t whqv write enable high to output valid (program) 10 2400 s write enable high to output valid (chip erase) 1 30 sec t ehqv chip enable high to output valid (program) 10 2400 s chip enable high to output valid (chip erase) 1 30 sec
19/24 M59BW102 figure 14. data polling dq7 ac waveform ai02771 e g w a0-a15 dq7 ignore valid dq0-dq6/ dq8-dq15 address data output valid tavqv tehq7v tglqv twhq7v valid tq7vqv dq7 data polling (last) cycle memory array read cycle data polling read cycles last write cycle of program or erase instruction telqv note: ale must be high.
M59BW102 20/24 figure 15. data polling flowchart read dq5 & dq7 at valid address start read dq7 fail pass ai01369b dq7 = data yes no yes no dq5 = 1 dq7 = data yes no figure 16. data toggle flowchart read dq2, dq5 & dq6 start read dq2, dq6 fail pass ai01873 dq2, dq6 = toggle no no yes yes dq5 = 1 no yes dq2, dq6 = toggle table 20. program, erase times and program, erase endurance cycles (t a = 0 to 70c; v cc = 3.0v to 3.6v) parameter M59BW102 unit min typ typical after 100k w/e cycles chip erase (preprogrammed) 0.7 0.7 sec chip erase 1.5 1.5 sec chip program 0.7 0.7 sec word program 10 10 s program/erase cycles 100,000 cycles
21/24 M59BW102 figure 17. data toggle dq6, dq2 ac waveforms ai02772 e g w a0-a15 dq6,dq2 tavqv stop toggle last write cycle of program of erase instruction valid valid valid ignore data toggle read cycle memory array read cycle twhqv tehqv telqv tglqv data toggle read cycle dq0-dq1,dq3-dq5,dq7/ dq8-dq15 note: all other timing are as a normal read cycle; aile must be high.
M59BW102 22/24 table 21. ordering information scheme for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the st sales office nearest to you. example: M59BW102 25 n 1 t device type m59 architecture b = burst mode operating voltage w = v cc = 2.7 to 3.6v device function 102 = 1 mbit (64kb x16) speed 25 = 25 ns sequential cycle time, 55 ns random access time package n = tsop40: 10 x 14 mm temperature range 1 = 0 to 70 c option t = tape & reel packing
23/24 M59BW102 figure 18. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline drawing is not to scale. tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1 a table 22. tsop40 - 40 lead plastic thin small outline, 10 x 14 mm, package mechanical data symb mm inches typ min max typ min max a 1.20 0.0472 a1 0.05 0.15 0.0020 0.0059 a2 0.95 1.05 0.0374 0.0413 b 0.17 0.27 0.0067 0.0106 c 0.10 0.21 0.0039 0.0083 d 13.80 14.20 0.5433 0.5591 d1 12.30 12.50 0.4843 0.4921 e 9.90 10.10 0.3898 0.3976 e0.50 C C 0.0197 C C l 0.50 0.70 0.0197 0.0276 a 0 5 0 5 n40 40 cp 0.10 0.0039
M59BW102 24/24 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics a 2000 stmicroelectronics - all rights reserved all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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